Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management
Matthew Rowlingsa, Andy M. Tyrrell and Martin A. Trefzerb
Department of Electronic Engineering University of York York, United Kingdom
amatthew.rowlings@york.ac.uk
bmartin.trefzer.york.ac.uk
ABSTRACT
Fabrication issues throttle VLSI designs with pessimistic design constraints and speed-grade device binning necessary to avoid failure of devices. We propose that a on chip monitoring system (a Nervous System) can reduce this margin by automatically sensing and reacting to failures and environmental changes at runtime. We demonstrate that pessimistic margins in the FPGA tools allow our test circuit to be overclocked by twice the maximum design tool frequency and run at 50 °C above its maximum operating temperature without error. The Configurable Intelligence Array is introduced as a low-overhead intelligence platform and used for a prototype neural circuit that can close the loop between a timing-fault detector and a programmable Phase Locked Loop (PLL) oscillator.
