Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design
Hao-Yu Chi1, Han-Chung Chang1,b, Chih-Hsin Yang2,a, Chien-Nan Liu1 and Jing-Yang Jou2,b
1Institute of Electronics, National Chiao Tung University, Hsinchu City, Taiwan, ROC
alogger1006.ee07g@nctu.edu.tw
bhcchang.ee07g@nctu.edu.tw
cjimmyliu@nctu.edu.tw
2Department of Electrical Engineering, National Central University, Jungli City, Taiwan, ROC
a18spin@gmail.com
bjyjou@ee.ncu.edu.tw
ABSTRACT
Analog layout is often considered as a difficult task because many layout-dependent effects will impact final circuit performance. In the literature, many automation techniques have been proposed for analog placement and routing respectively. However, very few works are able to consider the two steps simultaneously to obtain the best performance and cost after layout. Most of the routing-aware placement techniques optimize the layout results based on an assumed routing result, which may be quite different to the final layout. In this work, we proposed an automatic two-step layout methodology for analog circuits to alleviate the performance loss during layout process. Instead of using a rough routing prediction during placement stage, a crossing-aware global routing technique is first performed to provide an accurate routing resource estimation of the given compact placement. Then, the improved CDL-based layout migration technique is adopted to do a fast adjustment on the placement and routing to reduce the difference between estimation and final layout while keeping the optimality of the given placement. As shown in the experimental results, the proposed methodology is able to improve the accuracy of routing resource estimation thus improving the final layout quality and circuit performance.
