Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design
Jyotishman Saikia1,a, Shihui Yin1, Sai Kiran Cherupally1, Bo Zhang2, Jian Meng1, Mingoo Seok2 and Jae-sun Seo1,b
1School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA
2Department of Electrical Engineering, Columbia University, New York, NY, USA
ajsaikia@asu.edu
bjaesun.seo@asu.edu
ABSTRACT
In-memory computing (IMC) has been demonstrated as a promising technique to significantly improve energy-efficiency for deep neural network (DNN) hardware accelerators. However, designing one involves setting many design variables such as the number of parallel rows to assert, analog-to-digital converter (ADC) at the periphery of memory sub-array, activation/weight precisions of DNNs, etc., which affect energy-efficiency, DNN accuracy, and area. While individual IMC designs have been presented in the literature, they have not investigated this multi-dimensional design optimization. In this paper, to fill this knowledge gap, we present a SRAM-based IMC hardware modeling and optimization framework. A unified systematic study closely models IMC hardware, and investigates how a number of design variables and nonidealities (e.g. device mismatch and ADC quantization) affect the DNN accuracy of IMC design. To maintain high DNN accuracy for the IMC SRAM hardware, it is shown that the number of activated rows, ADC resolution, ADC quantization range, and different sources of variability/noise need to be carefully selected and cooptimized with an underlying DNN algorithm to implement.
Keywords: In-memory Computing, Deep Neural Networks, SRAM, Modeling, Optimization.
