Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming
Christopher Müncha and Mehdi B. Tahoorib
Department of Computer Science Karlsruhe Institute of Technology (KIT) Karlsruhe, Germany
achristopher.muench@kit.edu
bmehdi.tahoori@kit.edu
ABSTRACT
Neuromorphic architectures based on emerging resistive memories are in the spotlight of today’s research as they are able to solve complex problems with an unmatched efficiency. In particular, resistive approaches offer multiple advantages over CMOS-based designs. Most prominently they are non-volatile and offer small device footprints in addition to very low power operation. However, regular memory testing used for conventional resistive Random Access Memory (RAM) architectures cannot detect all possible faults in the synaptic operations done in a resistive neuromorphic architecture. At the same time, testing all neuromorphic operations from the logic testing perspective is infeasible. In this paper we propose to use reference resistance trimming for the test phase and derive a generic test sequence to detect all the faults impacting the neuromorphic operations based on an extensive defect injection analysis. By exploiting the resistive nature of the underlying architecture, we are able to reduce the testing time from an exponential complexity necessary for a conventional logic testing approach to a linear complexity and reduce this by another 50% with the help of resistance trimming.
Keywords: In-Memory Computing, Memory Testing, Resistive Memories, Resistance Trimming.
