Scramble Cache: An Efficient Cache Architecture for Randomized Set Permutation
Amine Jaamoum1,a, Thomas Hiscock1,b and Giorgio Di Natale2
1Univ. Grenoble Alpes, CEA, LETI MINATEC Campus, F-38054 Grenoble, France
aAmine.Jaamoum@cea.fr
bThomas.Hiscock@cea.fr
2Univ. Grenoble Alpes, CNRS, Grenoble INP*, TIMA, 38000 Grenoble, France
giorgio.di-natale@univ-grenoble-alpes.fr
ABSTRACT
Driven by the need of performance-efficient computations, a large number of systems resort to cache memories. In this context, cache side-channel attacks have been proven to be a serious threat for many applications. Many solutions and countermeasures exist in literature. Nevertheless, the majority of them do not cope with the constraints and limitations imposed by embedded systems. In this paper, we introduce a novel cache architecture that leverages randomized set placement to defeat cache side-channel analysis. A key property of this architecture is its low impact on performance and its small area overhead. We demonstrate that this countermeasure allows protecting the system against known cache side-channel attacks, while guaranteeing small overheads, making this solution suitable also for embedded systems.
