Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies
Shubham Rai1, Heinz Riener2, Giovanni De Micheli2 and Akash Kumar1
1CfAED Technische Universität Dresden, Germany
2Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
ABSTRACT
Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-based circuits, a large portion of a logic representation must be mapped to self-dual logic gates. This, in turn, depends upon how self-duality is preserved in the logic representation during logic optimization and technology mapping. In the present work, we develop Boolean size-optimization methods–a rewriting and a resubstitution algorithm using Xor-Majority Graphs (XMGs) as a logic representation aiming at better preserving self-duality during logic optimization. XMGs are more compact for both unate and binate logic functions as compared to conventional logic representations such as And-Inverter Graphs (AIGs) or Majority- Inverter Graphs (MIGs). We evaluate the proposed algorithm over crafted benchmarks (with various levels of self-duality) and cryptographic benchmarks. For cryptographic benchmarks with a high self-duality ratio, the XMG-based logic optimisation flow can achieve an area reduction of up to 17% when compared to AIG-based optimization flows implemented in the academic logic synthesis tool ABC.
