HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
Dhananjaya Wijerathne1,a, Zhaoying Li1,b, Anuj Pathania2, Tulika Mitra1,c and Lothar Thiele3
1National University of Singapore
admd@comp.nus.edu.sg
bzhaoying@comp.nus.edu.sg
ctulika@comp.nus.edu.sg
2University of Amsterdam
a.pathania@uva.nl
3Swiss Federal Institute of Technology Zurich
thiele@ethz.ch
ABSTRACT
Coarse-Grained Reconfigurable Array (CGRA) has emerged as a promising hardware accelerator due to the excellent balance among reconfigurability, performance, and energy efficiency. The CGRA performance strongly depends on a highquality compiler to map the application kernels on the architecture. Unfortunately, the state-of-the-art compilers fall short in generating high quality mapping within an acceptable compilation time, especially with increasing CGRA size.We propose HiMap – a fast and scalable CGRA mapping approach – that is also adept at producing close-to-optimal solutions for multi-dimensional kernels prevalent in existing and emerging application domains. The key strategy behind HiMap’s efficiency and scalability is to exploit the regularity in the loop iteration dependencies by employing a virtual systolic array as an intermediate abstraction layer in a hierarchical mapping. Experimental results confirm that HiMap can generate application mappings that hit the performance envelope of the CGRA. HiMap offers 17.3x and 5x improvement in performance and energy efficiency of the mappings compared to the state-of-the-art. The compilation time of HiMap for nearoptimal mappings is less than 15 minutes for 64x64 CGRA while existing approaches take days to generate inferior mappings.
