AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators
Cheng Tana, Chenhao Xieb, Ang Lic, Kevin J. Barkerd and Antonino Tumeoe
Pacific Northwest National Laboratory, Richland, WA, USA
acheng.tan@pnnl.gov
bchenhao.xie@pnnl.gov
cang.li@pnnl.gov
dkevin.barker@pnnl.gov
eantonino.tumeo@pnnl.gov
ABSTRACT
Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units interconnected through a network-on-chip (NoC), provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). Unfortunately, designing a CGRA for a specific application domain involves enormous software/hardware engineering effort (e.g., designing the CGRA, map operations onto the CGRA, etc) and requires the exploration on a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc). In this paper, we propose AURORA* – a hardware/software codesign framework to automatically synthesize optimal CGRA given a set of applications of interest.
Keywords: CGRA, Domain-Specific Reconfigurable Accelerator, Software/Hardware Codesign.
