Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs
Yulhwa Kima, Hyungjun Kimb, Jihoon Parkc, Hyunmyung Ohd and Jae-Joon Kime
Pohang University of Science and Technology (POSTECH), Pohang, Republic of Korea
ayulhwa.kim@postech.ac.kr
bhyungjun.kim@postech.ac.kr
cjihoon.park@postech.ac.kr
dhyunmyung.oh@postech.ac.kr
ejaejoon@postech.ac.kr
ABSTRACT
Implementing binary neural networks (BNNs) on computing-in-memory (CIM) hardware has several attractive features such as small memory requirement and minimal overhead in peripheral circuits such as analog-to-digital converters (ADCs). On the other hand, one of the downsides of using BNNs is that it degrades the classification accuracy. Recently, ResNet-style BNNs are gaining popularity with higher accuracy than conventional BNNs. The accuracy improvement comes from the high-resolution skip connection which binary ResNets use to compensate the information loss caused by binarization. However, the highresolution skip connection forces the CIM hardware to use highbit ADCs again so that area and energy overhead becomes larger. In this paper, we demonstrate that binary ResNets can be also mapped on CIM with low-bit ADCs via aggressive partial sum quantization and input-splitting combined with retraining. As a result, the key advantages of BNN CIM such as small area and energy consumption can be preserved with higher accuracy.
Keywords: NN Accelerator, Computing In Memory, Analog Computing, Hardware-Nn Co-Design.
