MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA
Takashi Imagawa1,a, Jaehoon Yu2, Masanori Hashimoto3 and Hiroyuki Ochi1,b
1Ritsumeikan University, Shiga, Japan
atakac-i@fc.ritsumei.ac.jp
bh-ochi@fc.ritsumei.ac.jp
2Tokyo Institute of Technology, Tokyo, Japan
yu.jaehoon@artic.iir.titech.ac.jp
3Osaka University, Osaka, Japan
hasimoto@ist.osaka-u.ac.jp
ABSTRACT
This paper proposes a technology mapping algorithm for implementing application circuits on via-switch FPGA (VSFPGA). The via-switch is a novel non-volatile and rewritable memory element. Its small footprint and low parasitic RC are expected to improve the area- and energy-efficiency of an FPGA system. Some unique features of the VS-FPGA require a dedicated technology mapping strategy for implementing application circuits with maximum energy-efficiency. One of the features is the small ratio of logic blocks to arithmetic blocks (ABs). Given an application circuit, the proposed algorithm first detects word-wise circuit elements, such as MUXs. These elements are evaluated with an index of how resource utilization and fan-out change when the corresponding element is implemented with AB. All these elements are sorted in descending order based on this index. According to this order, each element is mapped to AB one by one, and synthesis and evaluation are repeated iteratively until satisfying given design constraints. The experimental results show that resource utilization and maximum fan-out can be reduced by about 30% to 50% and 12% to 87%, respectively. The proposed algorithm is not limited to the VS-FPGA and is expected to improve computation density and energy-efficiency of various FPGAs dedicated to compute-intensive signal processing applications.
Keywords: SRAM-Based FPGA, CAD, EDA, Design-Space Exploration.
