Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup
Chun-Chang Yu1,a, Yu Hen Hu2, Yi-Chang Lu1 and Charlie Chung-Ping Chen1
1Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan
ad00943036@ntu.edu.tw
2Department of Electrical and Computer Engineering University of Wisconsin - Madison Madison, USA
ABSTRACT
An energy-efficient instruction cache lookup technique with low area overheads is proposed. The key concept of this Dynamic Early Tag Lookup (DETL) method is to exploit the presence of instruction fetch-bubble cycles. In a fetch-bubble cycle, the index of the matching cache set can be determined earlier. Hence, the dynamic energy for parallel memory accesses to irrelevant cache banks can be saved. We implemented the proposed DETL algorithm on a 4-way set-associative instruction cache in a RISC-V micro-architecture, and tested its performance using the SPEC CPU2006 benchmark suite. The experiment results showed a 19.38% dynamic power reduction with an area overhead smaller than 0.1%.
Keywords: Dynamic Early Tag Lookup, Energy-Efficient, Instruction Cache, Processor Architecture.
