Risk-Aware Cost-Effective Design Methodology for Integrated Circuit Locking
Yinghua Hua, Kaixin Yangb, Subhajit Dutta Chowdhuryc and Pierluigi Nuzzod
Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA
ayinghuah@usc.edu
bkaixinya@usc.edu
cduttacho@usc.edu
dnuzzo@usc.edu
ABSTRACT
We introduce a systematic framework for logic locking of integrated circuits based on the analysis of the sources of information leakage from both the circuit and the locking scheme and their formalization into a notion of risk that can guide the design against existing and possible future attacks. We further propose a two-level optimization-based methodology to generate locking strategies minimizing a cost function and balancing security, risk, and implementation overhead, out of a collection of locking primitives. Optimization results on a set of case studies show the potential of layering multiple locking primitives to provide high security at significantly lower risk.
Keywords: Hardware Security, Logic Locking, Risk Modeling.
