Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure
Ravi Ledallaa, Debjit Sinhab, Adil Bhanjic, Chaobo Lid, Gregory Schaeffere, Hemlata Guptaf and Jennifer Basileg
IBM Systems (EDA), Poughkeepsie, USA
aravc@us.ibm.com
bdebjitsinha@yahoo.com
cadil@us.ibm.com
dlich@us.ibm.com
egmschaef@us.ibm.com
fguptah@us.ibm.com
gbasile@us.ibm.com
ABSTRACT
This paper presents an approach to dynamically generating representative external driving cell and external wire parasitic assertions for the ports of sub-blocks of a hierarchical design. The assertions are based on a technology lookup table and use attributes of the port and the hierarchical wire connected to the port as keys. A concept of reverse timing calculation at the input of the driving cell is described that facilitates the approach to drive efficient timing optimization of boundary paths of design sub-blocks. Experimental results in an industrial timing environment demonstrate significantly improved timing optimization accuracy when compared to prior work.
Keywords: Timing Analysis, Assertions, Hierarchical Timing.
