Efficient Hardware-assisted Out-place Update for Persistent Memory
Yifu Deng1,a, Jianhui Yue1,b, Zhiyuan Lu1,c and Yifeng Zhu2
1Computer Science, Michigan Technological University, Houghton, Michigan, USA
ayifud@mtu.edu
bjyue@mtu.edu
czhlu@mtu.edu
2Electrical & Computer Engineering, University of Maine, Orono, Maine, USA
yifeng.zhu@maine.edu
ABSTRACT
Shadow paging can guarantee crash consistency for Persistent Memory (PM). However, shadow paging requires the use of an address mapping table to track shadow pages, and frequent accesses to this table introduce significant performance overhead. In addition, maintaining crash consistency at the granularity level of a page causes a large amount of unnecessary write traffic. This paper proposes a novel hardware-assisted fine-grained out-place-update scheme at the granularity level of a cacheline to efficiently support crash consistency for PM. Our design fully leverages the Address Indirection Table (AIT) available in commodity PM to implement remapping. To ensure the atomicity and durability of AIT updates, we propose two policies: eager persisting and lazy persisting. We also employ overflow log to handle the eviction of speculative AIT cache entries upon an overflow in the AIT cache. Evaluation results based on multicore workloads demonstrate that our proposed scheme can improve the transaction throughput over the state-of-the-art design by 24.0% on average.
Keywords: Computer Architecture, Persistent Memory, Crash Consistency, Logging, Shadow Paging.
