SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays
Ramon Canal1, Yiannakis Sazeides2 and Arkady Bramni3
1Universitat Politècnica de Catalunya Barcelona, Spain
rcanal@ac.upc.edu
2University of Cyprus Nicosia, Cyprus
yanos@cs.ucy.ac.cy
3Intel Corp. Haifa, Israel
arkady.bramnik@intel.com
ABSTRACT
This work proposes an SRAM array with built-in real-time error detection (RTD) capabilities. Each cell in the new RTD-SRAM array computes its part of the real-time parity of an SRAM array column on-the-fly. RTD based arrays detect a fault right away after it occurs, rather than when it is read. RTD, therefore, breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use on-the-fly error detection and correction. The paper presents an analysis and optimization of an RTD-SRAM and its application to a tag array. Compared to a state-of-the-art tag array protection, the evaluated scheme has comparable error detection and correction strength and, depending on the array dimensions, the access time is reduced by 5% to 18%, energy by 20% to 40% and area up to 30%.
Keywords: Reliability, Sram Array, Tag Array, Error Detection And Correction, Real-Time Error Detection (RTD).
