NoC Performance Model for Efficient Network Latency Estimation
Oumaima Matoussi
Université Paris-Saclay, CEA, List, F-91120, Palaiseau, France
Oumaima.MATOUSSI@cea.fr
ABSTRACT
We propose a flexible light-weight and parametric NoC model designed for fast performance estimation at early design stages. Our NoC model combines the benefits of both analytical and simulation-based NoC models. Our NoC features an abstract router model whose buffers are updated at runtime with information about the actual traffic. This traffic information is fed to a closed-form expression that computes packet latency and that accounts for network contention at a router basis. We evaluated our hybrid NoC model in terms of estimation accuracy and simulation speed. We compared the simulation results to the ones obtained with a cycle accurate NoC simulator called Garnet. Our NoC model achieves less than 17% error in average network latency estimation and attains up to 14⨯ speedup for a 8⨯8 mesh.
Keywords: NoC Modeling and Simulation, Network Contention, Network Latency Estimation, On-Chip Interconnect.
