Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints
Zhifeng Lin1, Yanyue Xie2, Gang Qian3, Jianli Chen1,3,a, Sifei Wang3, Jun Yu3 and Yao-Wen Chang4
1Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou 350108, China
2Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
3State Key Lab of ASIC & System, Fudan University, Shanghai 200433, China
4Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
achenjianli@fudan.edu.cn
ABSTRACT
Modern FPGAs often contain heterogeneous architectures and clocking resources which must be considered to achieve desired solutions. As the design complexity keeps growing, placement has become critical for FPGA timing closure. In this paper, we present an analytical placement algorithm for heterogeneous FPGAs to optimize its worst slack and clock constraints simultaneously. First, a heterogeneity-aware and memory-friendly delay model is developed to accurately and rapidly assess each connection delay. Then, a two-stage clock region refinement method is presented to effectively resolve the clock and resource violations. Finally, we develop a novel timing-based co-optimization method to generate optimized placement without any clocking violations. Compared with the state-of-the-art placer based on the advanced commercial tool Xilinx Vivado 2021.1 with the Xilinx 7 Series FPGA architecture, our algorithm achieves the best worst slack and routed wirelength while satisfying all clock constraints.
