Scalar Replacement In the Presence of Multiple Write Accesses For High-Level Synthesis
Kenshu Seto
Department of Electrical, Electronic and Communication Engineering Tokyo City University, Tokyo, Japan
ABSTRACT
High-level synthesis (HLS) reduces design time of domain-specific accelerators from loop nests. Usually, naive usage of HLS leads to accelerators with insufficient performance, so very time-consuming manual optimizations of input programs are necessary in such cases. Scalar replacement is a promising automatic memory access optimization that removes redundant memory accesses. However, it cannot handle loops with multiple write accesses to the same array, which poses a severe limitation of its applicability. In this paper, we propose a new memory access optimization technique that breaks the limitation. Experimental results show that the proposed method achieves 2.1x performance gain on average for the benchmark programs which the state-ofthe-art memory optimization techniques cannot optimize.
Keywords: High-Level Synthesis, Memory Access Optimization, Scalar Replacement
