ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification
Zhen Zhuang1, Xing Huang2, Genggeng Liu1,3,a, Wenzhong Guo1, Weikang Qian4 and Wen-Hao Liu5
1College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China
2Technical University of Munich, Munich, Bavaria, Germany
3State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
4University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China
5Block Implementation, ICD, Cadence Design Systems, Austin, TX, USA
aliu genggeng@126.com
ABSTRACT
As the scale of VLSI circuits increases rapidly, multi-FPGA prototyping systems have been widely used for logic verification. Due to the limited number of connections between FPGAs, however, the routability of prototyping systems is a bottleneck. As a consequence, timing division multiplexing (TDM) technique has been proposed to improve the usability of prototyping systems, but it causes a dramatic increase in system delay. In this paper, we propose ALIFRouter, a practical architecture-level inter-FPGA router, to improve the chip performance by reducing the corresponding system delay. ALIFRouter consists of three major stages, including i) routing topology generation, ii) TDM ratio assignment, and iii) system delay optimization. Additionally, a multi-thread parallelization method is integrated into the three stages to improve the efficiency of ALIFRouter. With the proposed algorithm, major performance indicators of multi-FPGA systems such as signal multiplexing ratio can be improved significantly.
