Leveraging Processor Modeling and Verification for General Hardware Modules
Yue Xinga, Huaixi Lub, Aarti Guptac and Sharad Malikd
Princeton University, Princeton, USA
ayuex@princeton.edu
bhuaixil@princeton.edu
caartig@princeton.edu
dsharad@princeton.edu
ABSTRACT
For processors, an instruction-set-architecture (ISA) provides a complete functional specification that can be used to formally verify an implementation. There has been recent work in specifying accelerators using formal instruction sets, referred to as Instruction-Level Abstractions (ILAs), and using them to formally verify their implementations by leveraging processor verification techniques. In this paper, we generalize ILAs for specification of general hardware modules and formal verification of their RTL implementations. This includes automated generation of a complete set of functional (not including timing) specification properties using the ILA instructions. We address the challenges posed by this generalization and provide several case studies to demonstrate the applicability of this technique, including all the modules in an open-source 8051 micro-controller. This verification identified three bugs and completed in reasonable time.
