Understanding Power Consumption and Reliability of High-BandwidthMemory with Voltage Underscaling
Seyed Saber Nabavi Larimi1,2, Behzad Salami1,5, Osman S. Unsal1, Adrián Cristal Kestelman1,2,3, Hamid Sarbazi-Azad4 and Onur Mutlu5
1BSC
2UPC
3CSIC-IIIA
4SUT and IPM
5ETH Zürich
ABSTRACT
Modern computing devices employ High-Bandwidth Memory (HBM) to meet their memory bandwidth requirements. An HBM-enabled device consists of multiple DRAMlayers stacked on top of one another next to a compute chip (e.g. CPU, GPU, and FPGA) in the same package. Although such HBM structures provide high bandwidth at a small form factor, the stacked memory layers consume a substantial portion of the package’s power budget. Therefore, power-saving techniques that preserve the performance of HBM are desirable. Undervolting is one such technique: it reduces the supply voltage to decrease power consumption without reducing the device’s operating frequency to avoid performance loss. Undervolting takes advantage of voltage guardbands put in place by manufacturers to ensure correct operation under all environmental conditions. However, reducing voltage without changing frequency can lead to reliability issues manifested as unwanted bit flips.
Keywords: High-Bandwidth Memory, Power Consumption, Voltage Scaling, Fault Characterization, Reliability.
