Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols
Anirudh Mohan Kaushika and Hiren Patelb
Electrical and Computer Engineering Department University of Waterloo, Waterloo, Canada
aanirudh.m.kaushik@uwaterloo.ca
bhiren.patel@uwaterloo.ca
ABSTRACT
We present SYNTHIA, an open and automated tool for synthesizing predictable and high-performance snooping busbased cache coherence protocols for multi-core processors in multi-processor system-on-chips (MPSoCs) deployed in real-time systems. SYNTHIA automates the complex analysis associated with designing predictable and high-performance cache coherence protocols, and constructs new states (transient states) and corresponding transitions that achieve predictability and performance. We use SYNTHIA to construct complete protocol implementations from simple specifications of common protocols (MSI, MESI, and MOESI protocols). We validated the correctness, predictability, and performance guarantees of the generated protocol implementations from SYNTHIA using manually implemented versions, and a micro-architectural simulator.
