Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM
Lizhou Wu1,a, Siddharth Rao3,a, Mottaqiallah Taouil1,2,b, Erik Jan Marinissen3,b, Gouri Sankar Kar3,c and Said Hamdioui1,2,c
1TUDelft, Delft, The Netherlands
2CognitiveIC, Delft, The Netherlands
aLizhou.Wu@tudelft.nl
bM.Taouil@tudelft.nl
cS.Hamdioui@tudelft.nl
3IMEC, Leuven, Belgium
aSiddharth.Rao@imec.be
bErik.Jan.Marinissen@imec.be
cGouri.Kar@imec.be
ABSTRACT
Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60nm to 120nm; the results reveal that the occurrence probability of IM state strongly depends on the switching direction, device size, and applied bias voltage. To test such defect, appropriate fault models are needed. Therefore, we use the advanced device-aware modeling approach, where we first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, we use a systematic fault analysis to accurately validate a theoretically predefined fault space and derive realistic fault models. Our simulation results show that the IM state defect causes intermittent write transition faults. This paper also demonstrates that the conventional resistor-based fault modeling and test approach fails in appropriately modeling IM defects, and hence incapable of detecting such defects.
