HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms
Haichang Yanga, Zhaoshi Lib, Jiawei Wangc, Shouyi Yind, Shaojun Weie and Leibo Liuf
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
ayanghc18@mails.tsinghua.edu.cn
blizhaoshi@tsinghua.edu.cn
cclaire wang@tsinghua.edu.cn
dyinsy@tsinghua.edu.cn
ewsj@tsinghua.edu.cn
fliulb@tsinghua.edu.cn
ABSTRACT
In-memory key-value store (KVS) has become crucial for many large-scale Internet services providers to build highperformance data centers. While most of the state-of-the-art KVS systems are optimized for read-intensive applications, a wide range of applications have been proven to be insert-intensive or scanintensive, which scale poorly with the current implementations. With the availability of FPGA-based smart NICs in data centers, hardware-aided and hardware-based KVS systems are gaining their popularity. In this paper, we present HeteroKV, a scalable line-rate KVS on heterogeneous CPU-FPGA platforms, aiming to provide high throughput in read-, insert- and scan-intensive scenarios. To achieve this, HeteroKV leverages a heterogeneous data structure consisting of a b+ tree, whose leaf nodes are cache-aware partitioned hash tables. Experiments demonstrate HeteroKV’s high performance in all scenarios. Specifically, a single node HeteroKV is able to achieve 430M, 315M and 15M key-value operations per second in read-, insert- and scan-intensive scenarios respectively, which are more than 1.5x, 1.4x and 5x higher than state-of-the-art implementations.
Keywords: In-Memory KVS, Hardware-Acceleration.
