Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies
Youngbog Yoon1,a, Daeyong Han1,b, Shinho Chu1,c, Sangho Lee1,d, Jaeduk Han2 and Junhyun Chun1,e
1DRAM Design Team SK Hynix Icheon, Korea
ayoungbog.yoon@sk.com
bdaeyoung.han@sk.com
cshinho.chu@sk.com
dsangho2.lee@sk.com
ejunhyun.chun@sk.com
2Electronic Engineering Hanyang University Seoul, Korea
jdhan@hanyang.ac.kr
ABSTRACT
This paper introduces a physical layout design methodology that produces DRC-clean, area-efficient, and programmable layouts of digital circuits in advanced DRAM processes. The proposed methodology automates the layout generation process to enhance design productivity, while still providing rich customization for efficient area and routing resource utilizations. Process-specific parameterized cells (PCells) are combined with process-independent place-and-route functions to automatically generate area-efficient and programmable layouts. Routing grids are optimized to enhance the area and routing efficiency. The proposed method reduced the design time of digital layouts by 80% compared to a manual design with high layout qualities, significantly enhancing the design productivity.
Keywords: DRAM, Standard Cells, Layout, Design Automation, Templates.
