Adaptive Body Bias for A 0.4V Operable Mpsoc in 22Fdx as an Example for Big Data Handling

Christian Mayr
Technische Universität Dresden, DE


One of the hottest buzzwords today is big data, i.e. the massive amounts of data that are produced by an ever expanding number of sensors across disciplines from archaeology to soccer. Some examples: in 2016, the amount of data transmitted globally for the first time exceeded a Zettabyte (1021), using up about 10% of the world energy supply. In 2015, the number of image sensors has risen above the number of humans on earth.

Thus, there is a need for dedicated data processing/machine learning chips that handle this load automatedly and reduce it to a data extract usable by humans. Deployment of these chips can be anywhere along the processing chain, e.g. integrated with the sensor interface to reduce data load at the source or as data aggregator in a server farm.

Prof. Mayr will give an overview of the multi-processor systems-on-chip (MPSoC) and sensor interfacing developed at his chair. As some of the first MPSoCs in 22nm FDSOI which use adaptive body biasing to compensate for process variability, they operate as low as 0.4V. Through a combination of dedicated accelerators (e.g. for machine learning) and conventional CPUs, these MPSoCs achieve an optimal compromise between energy efficiency and configurability. Applications pursued at the chair include: sensor nodes for the tactile internet, autonomous driving, neural implants and brain simulation.