IC Verification: How Formal Reduces Fault Analysis for ISO 26262
Dirk Hansen
Mentor, DE
ABSTRACT
The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult. Unlike simulation where it is never known if the design has been simulated enough or given enough input, formal verification conclusively determines if faults are safe or not, making the failure rates from formal analysis more than an arbitrary number determined by fault simulation. Formal analysis tools that apply SLEC techniques are an ideal solution for fault pruning, fault analysis, and determining diagnostic coverage. In this part of the workshop we will define how to use formal verification for static and transient fault analysis to generate ISO 26262 safety metrics, first describing fault pruning and then the more sophisticated fault injection using SLEC.
