Exploiting On‐chip Power Management for Side‐Channel Security
Arvind Singh1,a, Monodeep Kar1,b, Sanu Mathew2,d, Anand Rajan2,e, Vivek De2,f and Saibal Mukhopadhyay1,c
1Georgia Institute of Technology
arathorearvind19@gatech.edu
bmonodeepkar@gatech.edu
csaibal@ece.gatech.edu
2Intel Labs
dsanu.mathew@intel.com
eanand.rajan@intel.com
fvivek.de@intel.com
ABSTRACT
The high‐performance and energy‐efficient encryption engines have emerged as a key component for modern System‐On‐Chip (SoC) in various platforms including servers, desktops, mobile, and IoT edge devices. A key bottleneck to secure operation of encryption engines is leakage of information through various side‐channels. For example, an adversary can extract the secret key by performing statistical analysis on measured power and electromagnetic (EM) emission signatures generated by the hardware during encryption. Countermeasures to such side‐channel attacks often come at high power, area, or performance overheads. Therefore, design of side‐channel secure encryption engines is a critical challenge for high‐performance and/or power‐/energy efficient operations. This paper reviews that although low‐power requirement imposes critical challenge for side‐channel security, but circuit techniques traditionally developed for power management also present new opportunities for side‐channel resistance. As a case study, we review the feasibility of using integrated voltage regulator and dynamic voltage frequency scaling normally used for efficient power management, for increasing power‐side‐channel resistance of AES engines. The hardware measurement results from test‐chip fabricated in 130nm process are presented to demonstrate the impact of power management circuits on side‐channel security.
Keywords: Integrated Voltage Regulators, Side‐channel Attacks, Countermeasures, Voltage Dithering, Cryptography.
