Smart Instruction Codes for In‐Memory Computing Architectures Compatible with Standard SRAM Interfaces
Maha Koolia, Henri‐Pierre Charlesb, Clement Touzetc, Bastien Giraudd and Jean‐Philippe Noele
Univ. Grenoble Alpes, CEA, LETI, F‐38000 Grenoble
aMaha.Kooli@cea.fr
bHenri-Pierre.Charles@cea.fr
cClement.Touzet@cea.fr
dBastien.Giraud@cea.fr
eJean-Philippe.Noel@cea.fr
ABSTRACT
This paper presents the computing model for In‐Memory Computing architecture based on SRAM memory that embeds computing abilities. This memory concept offers significant performance gains in terms of energy consumption and execution time. To handle the interaction between the memory and the CPU, new memory instruction codes were designed. These instructions are communicated by the CPU to the memory, using standard SRAM buses. This implementation allows (1) to embed In‐Memory Computing capabilities on a system without Instruction Set Architecture (ISA) modification, and (2) to finely interlace CPU instructions and in‐memory computing instructions.
