Large scale, high d ensity integration of All Spin Logic
Qi AN1,a, Sébastien Le Beux2,c, Ian O’Connor2,d and Jacques‐Olivier Klein1,b
1C2N, Université Paris‐Sud UMR CNRS 9001, Orsay, France
aanqi_91@sina.com
bjacques-olivier.klein@u-psud.fr
2INL, Ecole Centrale de Lyon, Lyon, France
csebastien.le-beux@ec-lyon.fr
dian.oconnor@ec-lyon.fr
ABSTRACT
Spintronics brings new features that make it a viable candidate technology to implement non‐conventional processing for new computing paradigms in an efficient way. The first milestone of the spintronics roadmap was the fabrication of hybrid systems where the data processing relies mostly on charge‐based electronics devices (CMOS), while the memory hierarchy is partially or totally replaced by MRAM. In the next step, spintronics can also be used for data processing, still in conjunction with CMOS. Nevertheless, replacing all the processing by pure spintronic circuits, without any charge current, remains the ultimate objective of spintronics. All spin logic (ASL) paves the way towards that goal, even if some CMOS control circuits are still necessary. However, as ASL does not rely on the same computing principle as CMOS, it is necessary to address some specific issues. Pure spin current propagates in every direction, including backwards in the presence of multiple inputs; and is divided when crossings are encountered. It combines mainly linearly, while logic operations require non‐linear binary decisions. Interconnect between logic gates requires directionality from inputs to outputs, and fanout with negligible signal attenuation. In this context, we develop new strategies for ASL modeling and logic design. We propose an architecture and a design strategy based on a high‐density array to address the specific issues of directionality, attenuation and linearity. Moreover, the feasibility is supported through the modeling and the simulation of its basic block. This implies modularity to simulate complex circuits, even when they are ahead of today’s experimental demonstrations.
Keywords: All spin logic, modeling, array architecture.
