Main memory organization trade‐offs with DRAM and STT-MRAM options based on gem5‐NVMain simulation frameworks
Manu Komalan1,a, Oh Hyung Rock1, Matthias Hartmann1,3,b, Sushil Sakhare1, Christian Tenlladoy2, José Ignacio Gómezy2, Gouri Sankar Kar1, Arnaud Furnemont1, Francky Catthoor1,2,c, Sophiane Sennix4,d, David Novox4,e, Abdoulaye Gamatiex4,f and Lionel Torres4,g
1IMEC, Leuven 3001, Belgium
aManu.Perumkunnil@imec.be
bMatthias.Hartmann@imec.be
cFrancky.Catthoor@imec.be
2Universidad Complutense de Madrid, Madrid 28040, Spain
3KU Leuven 3001, Belgium
4LIRMM, University of Montpellier, CNRS, Montpellier, France
dSophiane.Senni@lirmm.fr
eDavid.Novo@lirmm.fr
fAbdoulaye.Gamatie@lirmm.fr
gLionel.Torres@lirmm.fr
ABSTRACT
Current main memory organizations in embedded and mobile application systems are DRAM dominated. The everincreasing gap between today’s processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade‐offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT‐MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multicore architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.
Keywords: NVM, Main Memory, Selector, Bit cell, NVMain.
