An Energy‐Efficient and Error‐Resilient Server Ecosystem Exceeding Conservative Scaling Limits
Georgios Karakonstantis1, Panos Koutsovasilis2, Srikumar Venugopal3, Andreas Diavastos4 and George Papadimitriou5
1Konstantinos Tovletoglou Lev Mukhanov Hans Vandierendonck Dimitrios S. Nikolopoulos Queen's University Belfast Peter Lawthers A.M.C.C. Deutschland
2Manolis Maroudas Christos D. Antonopoulos Christos Kalogirou Nikos Bellas Spyros Lalis University of Thessaly
3IBM Research ‐ Ireland Arnau Prat‐Pérez Sparsity Alejandro Lampropulos Worldsensing Marios Kleanthous Meritorious
4Zacharias Hadjilambrou Panagiota Nikolaou Yiannakis Sazeides Pedro Trancoso University of Cyprus
5Manolis Kaliorakis Athanasios Chatzidimitriou Dimitris Gizopoulos University of Athens Shidhartha Das ARM Ltd.
ABSTRACT
The explosive growth of Internet‐connected devices will soon result in a flood of generated data, which will increase the demand for network bandwidth as well as compute power to process the generated data. Consequently, there is a need for more energy efficient servers to empower traditional centralized Cloud data‐centers as well as emerging decentralized data‐centers at the Edges of the Cloud. In this paper, we present our approach, which aims at developing a new class of micro‐servers ‐ the UniServer ‐ that exceed the conservative energy and performance scaling boundaries by introducing novel mechanisms at all layers of the design stack. The main idea lies on the realization of the intrinsic hardware heterogeneity and the development of mechanisms that will automatically expose the unique varying capabilities of each hardware. Low overhead schemes are employed to monitor and predict the hardware behavior and report it to the system software. The system software including a virtualization and resource management layer is responsible for optimizing the system operation in terms of energy or performance, while guaranteeing non‐disruptive operation under the extended operating points. Our characterization results on a 64‐bit ARMv8 micro‐server in 28nm process reveal large voltage margins in terms of Vmin variation among the 8 cores of the CPU chip, among three different sigma chips, and among different benchmarks with the potential to obtain up‐to 38.8% energy savings. Similarly, DRAM characterizations show that refresh rate and voltage can be relaxed by 35x and 5%, respectively, leading to 23.2% power savings on average.
