A WCET‐Aware Parallel Programming Model for Predictability Enhanced Multi‐core Architectures
Simon Reder1, Leonard Masing1, Harald Bucher1, Timon ter Braak2, Timo Stripf3 and Jürgen Becker1
1Karlsruhe Institute of Technology
2Recore Systems B.V.
3emmtrix Technologies GmbH
ABSTRACT
Increasing performance requirements for cyberphysical systems in real‐time applications raise the necessity to migrate to multi‐core processor systems. However, commercial of the shelf multi‐core systems are often inappropriate for the realtime domain and real‐time capable multi‐core programming models are rare. In this paper, we present a solution developed within the EU research project ARGO. By means of a predictabilityenhanced NoC‐based multi‐/many‐core architecture, we investigate hardware properties that can help to improve the predictability of the platform and the programming model. Both platform and programming model are complemented by a WCET‐aware Architecture Description Language (ADL). This enables a certain degree of hardware abstraction while preserving the relevant details for accurate multi‐core WCET analysis algorithms. Target platform and programming model are designed to be statically analyzable by multi‐core WCET computation tools, that are part of the automated WCET‐aware software parallelization tool flow developed in the ARGO project.
