Compiler‐Driven Error Analysis for Designing Approximate Accelerators
Jorge Castro‐Godínez1,2,a, Sven Esser1, Muhammad Shafique3, Santiago Pagani1,4 and Jörg Henkel1
1Chair for Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), Germany
2School of Electronics Engineering, Instituto Tecnológico de Costa Rica, Costa Rica
3Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria
4ARM Ltd., Cambridge, United Kingdomy
ajorge.castro-godinez@kit.edu
ABSTRACT
Approximate Computing has emerged as a design paradigm suitable to applications with inherent error resilience. This paradigm aims to reduce the associated computing costs (such as execution time, area, or energy) of exact calculations by reducing the quality of their results. Several approximate arithmetic circuits have been proposed, which can be used to implement hardware blocks such as approximate accelerators. However, to satisfy quality constraints in these accelerators, it is imperative to assess how the errors introduced by approximate circuits propagate through other exact and approximate computations, and finally accumulate at the output. This is, in particular, crucial to enable high‐level synthesis of approximate accelerators. This work proposes a compiler‐driven error analysis methodology to evaluate the behavior of errors generated from approximate adders in the design of approximate accelerators. We present CEDA, a tool to perform a static analysis of the error propagation. This tool uses #pragma‐based annotated C/C++ source code as input. With these annotations, exact additions are replaced by approximate ones during the code analysis to estimate the error at the output. The error estimations produced by our tool are comparable to those obtained through simulations.
Keywords: Approximate computing, error analysis, design tools.
