DeMAS: An Efficient Design Methodology for Building Approximate Adders for FPGA‐Based Systems

Bharath Srinivas Prabakaran1,a, Semeen Rehman1, Muhammad Abdullah Hanif1, Salim Ullah2, Ghazal Mazaheri3, Akash Kumar2 and Muhammad Shafique1,b
1Vienna University of Technology (TU Wien), Austria
abharath.prabakaran@tuwien.ac.at
bmuhammad.shafique@tuwien.ac.at
2Technische Universität Dresden, Germany
3University of California, Riverside, United States of America

ABSTRACT


The current state‐of‐the‐art approximate adders are mostly ASIC‐based, i.e., they focus solely on gate and/or transistor level approximations (e.g., through circuit simplification or truncation) to achieve area, latency, power and/or energy savings at the cost of accuracy loss. However, when these designs are synthesized for FPGA‐based systems, they do not offer similar reductions in area, latency and power/energy due to the underlying architectural differences between ASICs and FPGAs. In this paper, we present a novel generic design methodology to synthesize and implement approximate adders for any FPGA‐based system by considering the underlying resources and architectural differences. Using our methodology, we have designed, analyzed and presented eight different multi-bit adder architectures. Compared to the 16‐bit accurate adder, our designs are successful in achieving area, latency and power‐delay product gains of 50%, 38%, and 53%, respectively. We also compare our approximate adders to state‐of‐the‐art approximate adders specialized for ASIC and FPGA fabrics and demonstrate the benefits of our approach. We will make the RTL and behavioral models of our and state‐of‐theart designs open‐source at https://sourceforge.net/projects/approxfpgas/ to further fuel the research and development in the FPGA community and to ensure reproducible research.

Keywords: Approximate Computing, FPGA, Adders, LUTs, Optimization, Design Flow, Efficiency, Area, Power, Performance, CAD.



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