Towards Inter‐Vendor Compatibility of True Random Number Generators for FPGAs

Miloš Grujića, Bohan Yangb, Vladimir Rožićc and Ingrid Verbauwheded
imec‐COSIC, KU Leuven, Kasteelpark Arenberg 10, B‐3001 Leuven‐Heverlee, Belgium
amilos.grujic@esat.kuleuven.be
bbohan.yang@esat.kuleuven.be
cvladimir.rozic@esat.kuleuven.be
dingrid.verbauwhede@esat.kuleuven.be

ABSTRACT


True random number generators (TRNGs) are fundamental constituents of secure embedded cryptographic systems. In this paper, we introduce a general methodology for porting TRNG across different FPGA vendor families. In order to demonstrate our methodology, we applied it to the delay‐chain based TRNG (DC-TRNG) on Intel Cyclone IV and Cyclone V FPGAs. We examine vendor‐agnostic generality of the underlying DCTRNG principle and propose modifications to address differences in structure of FPGAs. Implementation of the DC‐TRNG on Cyclone IV uses 149 LEs (<0.1% of available resources) and has a throughput of 5Mbps, while on Cyclone V it occupies 230 ALMs (<1.5% of resources) with an output rate of 12.5 Mbps. The quality of the random bits produced by the DC‐TRNG on Intel Cyclone IV and V is further confirmed by using NIST statistical test suite.



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