MATIC: Learning Around Errors for Efficient Low‐Voltage Neural Network Accelerators
Sung Kim1,a, Patrick Howe1,b, Thierry Moreau2,d, Armin Alaghi2,e, Luis Ceze2,f and Visvesh Sathe1,c
1Paul G. Allen School of Computer Science and Engineering
asungk9@ee.washington.edu
bpdh4@ee.washington.edu
csathe@ee.washington.edu
2University of Washington, USA
dmoreau@cs.washington.edu
earmin@cs.washington.edu
fceze@cs.washington.edu
ABSTRACT
As a result of the increasing demand for deep neural network (DNN)‐based services, efforts to develop dedicated hardware accelerators for DNNs are growing rapidly. However, while accelerators with high performance and efficiency on convolutional deep neural networks (Conv‐DNNs) have been developed, less progress has been made with regards to fullyconnected DNNs (FC-DNNs). In this paper, we propose MATIC (Memory Adaptive Training with In‐situ Canaries), a methodology that enables aggressive voltage scaling of accelerator weight memories to improve the energy‐efficiency of DNN accelerators. To enable accurate operation with voltage overscaling, MATIC combines the characteristics of destructive SRAM reads with the error resilience of neural networks in a memory‐adaptive training process. Furthermore, PVT‐related voltage margins are eliminated using bit‐cells from synaptic weights as in‐situ canaries to track runtime environmental variation. Demonstrated on a low‐power DNN accelerator that we fabricate in 65 nm CMOS, MATIC enables up to 60‐80 mV of voltage overscaling (3.3× total energy reduction versus the nominal voltage), or 18.6× application error reduction.
Keywords: Deep neural networks, Voltage scaling, SRAM, Machine learning acceleration.
