ATPG Power Guards: On Limiting the Test Power below Threshold
Rohini Gulvea and Virendra Singhb
Computer Architecture and Dependable Systems Lab, Electrical Engineering, Indian Institute of Technology Bombay, India
arohini.gulve@iitb.ac.in
bviren@ee.iitb.ac.in
ABSTRACT
Modern circuits with high performance and low power requirements impose strict constraints on manufacturing test generation, particularly on timing test. Delay test is used for performance grading of the circuit. During the application of the test, power consumption has to be less than the functional threshold value, in order to avoid yield loss. This work proposes a new direction to generate power safe test without any changes in DFT (design for testability) structure or existing CAD (computeraided design) tools. We propose a virtual wrapper circuitry around the circuit under test (CUT), for test generation purpose, which acts as a shield to obtain power safe vectors. The wrapper prohibits the generation of test vector if power consumption exceeds the threshold limits.We consider analytical power models for power analysis of candidate test vector patterns. Experiments performed on benchmark circuits show power safe test generation without coverage loss.
