Designing Reliable Processor Cores in Ultimate CMOS and Beyond: a Double Sampling Solution
Thierry Bonnoita, Fraidy Bouesseb, Nacer‐Eddine Zergainohc and Michael Nicolaidisd
Univ. Grenoble Alpes, CNRS, Grenoble INP*, TIMA, 38000 Grenoble, France
athierry.bonnoit@univ-grenoble-alpes.fr
bfraidy.bouesse@univ-grenoble-alpes.fr
cnacer-eddine.zergainoh @univ-grenoble-alpes.fr
dmichael.nicolaidis@univ-grenoble-alpes.fr
ABSTRACT
The double sampling paradigm is an efficient method to protect the circuits against soft‐errors. But the data that are going out of the area protected by double sampling are still vulnerable. In this paper we proposed an architectural solution that uses three latches to remove those constraints and protect the area outside the double sampling domain without adding a buffer stage.
Keywords: Double sampling, Soft-errors, LEON3, Reliability.
