XNOR‐RRAM: A Scalable and Parallel Resistive Synaptic Architecture for Binary Neural Networks
Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seoa and Shimeng Yub
School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85281, USA
ajaesunseo@asu.edu
bshimengy@asu.edu
ABSTRACT
Recent advances in deep learning have shown that Binary Neural Networks (BNNs) are capable of providing a satisfying accuracy on various image datasets with significant reduction in computation and memory cost. With both weights and activations binarized to +1 or -1 in BNNs, the high‐precision multiply‐and‐accumulate (MAC) operations can be replaced by XNOR and bit‐counting operations. In this work, we propose a RRAM synaptic architecture (XNOR‐RRAM) with a bit‐cell design of complementary word lines that implements equivalent XNOR and bit‐counting operation in a parallel fashion. For large‐scale matrices in fully connected layers or when the convolution kernels are unrolled in multiple channels, the array partition is necessary. Multi‐level sense amplifiers (MLSAs) are employed as the intermediate interface for accumulating partial weighted sum. However, a low bit‐level MLSA and intrinsic offset of MLSA may degrade the classification accuracy. We investigate the impact of sensing offsets on classification accuracy and analyze various design options with different sub‐array sizes and sensing bit‐levels. Experimental results with RRAM models and 65nm CMOS PDK show that the system with 128×128 subarray size and 3-bit MLSA can achieve accuracies of 98.43% for MLP on MNIST and 86.08% for CNN on CIFAR‐10, showing 0.34% and 2.39% degradation respectively compared to the accuracies of ideal BNN algorithms. The projected energyefficiency of XNOR‐RRAM is 141.18 TOPS/W, showing ∼33X improvement compared to the conventional RRAM synaptic architecture with sequential row‐by‐row read‐out.
