A Novel Fault Tolerant Cache Architecture Based on Orthogonal Latin Squares Theory
Filippos Filippou1, Georgios Keramidas2,3, Michail Mavropoulos1 and Dimitris Nikolos1
1Department of Computer Engineering & Informatics, University of Patras, Patras, GR26500, Greece
2Think Silicon S.A., GR26505, Greece
3Computer & Informatics Engineering Department, Technological Educational Institute of Western Greece, GR30020, Greece
ABSTRACT
Aggressive dynamic voltage and frequency scaling is widely used to reduce the power consumption of microprocessors. Unfortunately, voltage scaling increases the impact of process variations on memory cells resulting in an exponential increase in the number of malfunctioning memory cells. As a result, various cache fault‐tolerant (CFT) techniques have been proposed. In this work, we propose a new CFT technique which applies a systematic redistribution (permutation) of the cache blocks (assuming various block granularity levels) within the cache structure using the orthogonal Latin Square concept and taking as input the location of the malfunctioning cells in the cache array. The aim of the redistribution is twofold. First, to uniformly distribute the faulty blocks to sets and second, to gather the faulty subblocks to a minimum number of blocks, so as the fault free blocks are maximized. Our evaluation results using the benchmarks of SPEC2006 suite, 100 memory fault maps, and four percentages of malfunctioning cells show that our proposal exhibits strong capability to reduce cache performance degradation especially in situations with high percentages of faulty cells and compares favorably to already known techniques.
