Approximate Quaternary Addition with the Fast Carry Chains of FPGAs
Sina Boroumand1, Hadi P. Afshar2 and Philip Brisk3
1University of Tehran, Tehran, Iran
s_boroumand@ut.ac.ir
2Qualcomm Research San Diego, USA
hpafshar@qti.qualcomm.com
3University of California, Riverside, Riverside, USA
philip@cs.ucr.edu
ABSTRACT
A heuristic is presented to efficiently synthesize approximate adder trees on Altera and Xilinx FPGAs using their carry chains. The mapper constructs approximate adder trees using an approximate quaternary adder as the fundamental building block. The approximate adder trees are smaller than exact adder trees, allowing more operators to fit into a fixed-area device, trading off arithmetic accuracy for higher throughput.
Keywords: Approximate Arithmetic, Adder tree, Ternary Adder, Quaternary Adder, FPGA.
