HME: A Lightweight Emulator for Hybrid Memory
Zhuohui Duana, Haikun Liub, Xiaofei Liaoc and Hai Jd
Services Computing Technology and System Lab/Cluster and Grid Computing Lab/Big Data Technology and System Lab
School of Computing Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, China
azhduan@hust.edu.cn
bhkliu@hust.edu.cn
cxfliao@hust.edu.cn
dhjin@hust.edu.cn
ABSTRACT
Emerging non‐volatile memory (NVM) technologies have been widely studied in recent years. Those studies mainly rely on cycle‐accurate architecture simulators because the commercial NVM hardware is still unavailable. However, current simulation approaches are either too slow, or cannot simulate complex and large‐scale workloads. In this paper, we propose a DRAM-based hybrid memory emulator, called HME, to emulate the performance characteristics of NVM devices. HME exploits hardware features available in commodity Non‐Uniform Memory Access (NUMA) architectures to emulate two kinds of memories: fast, local DRAM, and slower, remote NVM on other NUMA nodes. HME can emulate a wide range of NVM latencies by injecting software‐created memory access delays on the remote NUMA nodes. To evaluate the impact of hybrid memories on the application performance, we also provide application programming interfaces to allocate memory from NVM or DRAM regions. We evaluate the accuracy of the read/write delay injection models by using SPEC CPU2006 and compare the results with a state‐ofthe‐ art NVM emulator Quartz. Experimental results demonstrate that the average emulation errors of NVM read and write latencies are less than 5% in HME, which is much lower than Quartz. Moreover, the application performance overhead in HME is one order of magnitude lower than Quartz.
