HiMap: A Hierarchical Mapping Approach for Enhancing Lifetime Reliability of Dark Silicon Manycore Systems
Vijeta Rathore1,a, Vivek Chaturvedi1,b, Amit K. Singh2, Thambipillai Srikanthan1, Rohith R1, Siew-Kei Lam1 and Muhammad Shafique3
1School of Computer Science and Engineering, Nanyang Technological University (NTU), Singapore
avijeta001@e.ntu.edu.sg
bvchaturvedi@ntu.edu.sg
2School of Computer Science and Electronic Engineering, University of Essex, UK
a.k.singh@essex.ac.uk
3Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria
muhammad.shafique@tuwien.ac.at
ABSTRACT
Technology scaling into the nano‐scale CMOS regime has resulted in increased leakage and roadblock on voltage scaling, which has led to several issues like high power density and elevated on‐chip temperature. This consequently aggravates device aging, compromising lifetime reliability of the manycore systems. This paper proposes HiMap, a dynamic hierarchical mapping approach to maximize lifetime reliability of manycore systems while satisfying performance, power, and thermal constraints. HiMap is process variation‐ and aging‐aware. It comprises of two levels: (1) it identifies a region of cores suitable for mapping, and (2) it maps threads in the region and intersperses dark cores for thermal mitigation while considering the current health of the cores. Both the levels strive to reduce aging variance across the chip. We evaluated HiMap for 64‐core and 256‐core systems. Results demonstrate an improved system lifetime reliability by up to 2 years at the end of 3.25 years of use, as compared to the state‐of‐the-art.
Keywords: Lifetime, Reliability, Aging, Mapping, Manycore systems, Dark silicon, Process variation, Optimization.
