Ising‐PUF: A Machine Learning Attack Resistant PUF Featuring Lattice Like Arrangement of Arbiter‐PUFs
Hiromitsu Awano1 and Takashi Sato2
1VLSI Design and Education Center, The University of Tokyo Hongo 7‐3‐1, Bunkyo‐ku, Tokyo, Japan
awano@vdec.u-tokyo.ac.jp
2Graduate School of Informatics, Kyoto University, Yoshida‐honmachi, Sakyo‐ku, Kyoto, Japan
paper@easter.kuee.kyoto-u.ac.jp
ABSTRACT
A concept of Ising‐PUF, a novel PUF structure that utilizes chaotic behavior of mutually interacting small PUFs, is proposed. Ising‐PUF consists of a lattice like arrangement of small PUFs, each of which contains a spin register that stores the response of the small PUF, which also serves as a challenge of its neighbors. The spin patterns that develop along time determine the 1‐bit response of the Ising‐PUF. Utilizing statememorizing nature of the spin registers, Ising‐PUF attains a challenge hysteresis, i.e., allowing sequence of challenge inputs that continuously stimulate its chaotic behavior, which provides the drastically large challenge‐to‐response space. Experimental results demonstrate nearly ideal metrics; inter‐chip Hamming distance (HD) of 50.1% and inter‐environment HD of 2.26%. Further, Ising‐PUF is remarkably tolerant to machine learning attacks, demonstrating that, even with a deep neural network using a 50k training CRPs, the prediction accuracy remains 50%, which is comparable to a random guess.
