An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
Deepak M. Mathew1,a, Martin Schultheis1, Carl C. Rheinländer1, Chirag Sudarshan1, Christian Weis1,b, Norbert Wehn1,c and Matthias Jung2
1University of Kaiserslautern, Germany
adeepak@eit.uni-kl.de
bweis@eit.uni-kl.de
cwehn@eit.uni-kl.de
2Fraunhofer Institute for Experimental Software Engineering (IESE) Kaiserslautern, Germany
matthias.jung@iese.fraunhofer.de
ABSTRACT
DRAM technology is scaling aggressively that results in high leakage power, worse data retention time behavior, and large process variations. Due to these process variations, vendors provide large guard bands on various DRAM currents and timing specifications that are over pessimistic. Detailed knowledge on the DRAM retention behavior and currents for the average case allow to improve memory system performance and energy efficiency of specific applications by moving away from worst case behavior. In this paper, we present an advanced measurement platform to investigate off‐the‐shelf DDR4 DRAMs’ retention behavior, and to precisely measure various DRAM currents (IDDs and IPPs) at a wide range of operating temperatures. Error Checking and Correction (ECC) schemes are popular in correcting randomly scattered single bit errors. Since retention failures also occur randomly, ECCs can be used to improve DRAM retention behavior. Therefore, for the first time, we show the influence of ECC on the retention behavior of recent DDR4 DRAMs, and how it varies across various DRAM architectures considering detailed structure of the DRAM (true‐cell devices / mixed‐cell devices).
