Reconfigurable implementation of GF(2m) bit‐parallel multipliers
José L. Imaña
Department of Computer Architecture and Automation, Faculty of Physics, Complutense University, 28040 Madrid, Spain
jluimana@ucm.es
ABSTRACT
Hardware implementations of arithmetic operations over binary finite fields GF(2m) are widely used in several important applications, such as cryptography, digital signal processing and error‐control codes. In this paper, efficient reconfigurable implementations of bit-parallel canonical basis multipliers over binary fields generated by type II irreducible pentanomials f(y) = ym + yn+2 + yn+1 + yn + 1 are presented. These pentanomials are important because all five binary fields recommended by NIST for ECDSA can be constructed using such polynomials. In this work, a new approach for GF(2m) multiplication based on type II pentanomials is given and several post‐place and route implementation results in Xilinx Artix‐7 FPGA are reported. Experimental results show that the proposed multiplier implementations improve the area×time parameter when compared with similar multipliers found in the literature.
