Optimal DC/AC Data Bus Inversion Coding
Jan Lucasa, Sohan Lalb and Ben Juurlinkc
Embedded Systems Architecture TU Berlin Berlin, Germany
aj.lucas@tu-berlin.de
bsohan.lal@tu-berlin.de
cb.juurlink@tu-berlin.de
ABSTRACT
GDDR5 and DDR4 memories use data bus inversion (DBI) coding to reduce termination power and decrease the number of output transitions. Two main strategies exist for encoding data using DBI: DBI DC minimizes the number of outputs transmitting a zero, while DBI AC minimizes the number of signal transitions. We show that neither of these strategies is optimal and reduction of interface power of up to 6% can be achieved by taking both the number of zeros and the number of signal transitions into account when encoding the data. We then demonstrate that a hardware implementation of optimal DBI coding is feasible, results in a reduction of system power and requires only an insignificant additional die area.
Keywords: Data bus inversion, DDR4, GDDR5, power consumption, termination power.
