HyVE: Hybrid Vertex‐Edge Memory Hierarchy for Energy‐Efficient Graph Processing
Tianhao Huanga, Guohao Daib, Yu Wangc and Huazhong Yangd
TNLIST, Tsinghua University, Beijing, China
ahth14@mails.tsinghua.edu.cn
bdgh14@mails.tsinghua.edu.cn
cyu-wang@tsinghua.edu.cn
dyanghz@tsinghua.edu.cn
ABSTRACT
High energy consumption of conventional memory modules (e.g., DRAMs) hinders the further improvement of large scale graph processing's energy efficiency. The emerging metaloxide resistive random‐access memory (ReRAM) and ReRAM crossbar have shown great potential in providing the energy efficient memory module. However, the performance of ReRAMs suffers from data access patterns with poor locality and large amounts of written data, which are common in graph processing. In this paper, we propose a Hybrid Vertex‐Edge memory hierarchy, HyVE, to avoid random access and data written to ReRAM modules. With data allocation and scheduling over vertices and edges, HyVE reduces memory energy consumption by 69% compared with conventional memory system in graph processing. Moreover, we adopt a bank level power‐gating scheme to further reduce the stand-by power. Our evaluations show that the optimized design achieves at least 2.0x improvement of energy efficiency compared with DRAM‐based designs.
