ACCLIB: Accelerators as Libraries
Jacob R. Stevens1,a, Yue Du3, Vivek Kozhikkottu2 and Anand Raghunathan1,b
1Purdue University
asteven69@purdue.edu
braghunathan@purdue.edu
2Intel Corporation
vivek.kozhikkottu@intel.com
3IBM
ABSTRACT
Accelerator‐based computing, which has been a mainstay of System‐on‐Chips (SoCs) is of growing interest to a wider range of computing systems. However, the significant design effort required to identify a computational target for acceleration, design a hardware accelerator, verify the correctness of the accelerator, integrate the accelerator into the system, and rewrite applications to use the accelerator, is a major bottleneck to the widespread adoption of accelerator‐based computing. The classical approach to this problem is based on top‐down methodologies such as automatic HW/SW partitioning and high-level synthesis (HLS). While HLS has advanced significantly and is seeing increased adoption, it does not leverage the ability of experienced human designers to craft highly optimized RTL, nor does it leverage the growing body of already existing hardware accelerators. In this work, we propose ACCLIB, a design framework that allows software developers to utilize existing libraries of pre‐designed hardware accelerators automatically with no prior knowledge of the function of the accelerators, with minimal knowledge of hardware design, and with minimal design effort. To accomplish this, ACCLIB uses formal verification techniques to match a target software function with a functionally equivalent accelerator from a library of accelerators. It also generates the required HW/SW interfaces as well as the code necessary to offload the computation to the accelerator. We validate ACCLIB by applying it to accelerate six different applications using a library of hardware accelerators in just over one hour per application, demonstrating that the proposed approach has the potential to lower the barrier to adoption of accelerator‐based computing.
Keywords: Accelerator‐based computing, high‐level synthesis, interface synthesis, formal verification.
